When valid_in is ‘1’ it will accept serial input and that serial input goes for parallel output. After receiving eight bit of serial input this block converts the serial input to parallel output. Valid_out signal goes ‘1’ after receiving eight bytes of serial data & gives parallel data on the data_o. After valid_out goes high parity_out signal gives parity of the input data. Valid_out signal goes high on each eighth clock cycle & remain high for one cycle.
Below figure shows VHDL program for parity generator line 13 shows the XOR operation on all input bits. This will result in even parity bit generation as already mentioned in Boolean equation. Line 15 simply performs not operation of even parity generation, which means it's an odd parity generation. Vhdl programs - Free download as Word Doc (.doc), PDF File (.pdf), Text File (.txt) or read. A Parity generator creates the parity bit on the transmission side.
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